The Predictive Technology Model in the Late Silicon Era and Beyond
By Yu Cao, School of ECEE, Arizona State University, Yu.Cao@asu.edu | Asha Balijepalli, Global Foundries Inc. | Saurabh Sinha, School of ECEE, Arizona State University | Chi-Chao Wang, School of ECEE, Arizona State University | Wenping Wang, Vitesse Semiconductor Corp. | Wei Zhao, Qualcomm Inc.
Abstract
The aggressive scaling of CMOS technology has inevitably led to vastly increased power dissipation, process variability and reliability degradation, posing tremendous challenges to robust circuit design. To continue the success of integrated circuits, advanced design research must start in parallel with or even ahead of technology development. This new paradigm requires the Predictive Technology Model (PTM) for future technology generations, including nanoscale CMOS and post-silicon devices. This paper presents a comprehensive set of predictive modeling developments. Starting from the PTM of traditional CMOS devices, it extends to CMOS alternatives at the end of the silicon roadmap, such as strained Si, high-k/metal gate, and FinFET devices. The impact of process variation and the aging effect is further captured by modeling the device parameters under the influence. Beyond the silicon roadmap, the PTM outreaches to revolutionary devices, especially carbon-based transistor and interconnect, in order to support explorative design research. Overall, these predictive device models enable early stage design exploration with increasing technology diversity, helping shed light on the opportunities and challenges in the nanoelectronics era.
The Predictive Technology Model in the Late Silicon Era and Beyond
The Predictive Technology Model is an essential bridge between technology innovation and IC design exploration. By developing predictive model files for devices at the end of the silicon roadmap and beyond, it enables early stage design research ahead of technology development. Coupled with circuit simulation tools, the PTM significantly improves design productivity, providing the key insight into the relationship between technology/design choices and circuit performance in the nanoscale regime. This comprehensive review on the development of the PTM is an invaluable resource for foundry technologists or circuit design researchers, helping illustrate the diverse opportunities and challenges in the nanoelectronics era.
